Please use this identifier to cite or link to this item:
http://hdl.handle.net/10263/2574| Title: | Hierarchical partitioning of VLSI floorplans by staircases |
| Authors: | Majumder, S Sur Kolay, Susmita Bhattacharya, Bhargab B Das, S K |
| Keywords: | Floorplanning Global routing Network flow N P completeness Balanced bipartitioning |
| Issue Date: | 2007 |
| Citation: | ACM Transactions on design automation of electronic systemsV12,P141-159 |
| URI: | http://hdl.handle.net/10263/2574 |
| Appears in Collections: | Mathematics and Statistics |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| hierarchical partitioning.pdf | 2.99 MB | Adobe PDF | View/Open |
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