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Please use this identifier to cite or link to this item: http://hdl.handle.net/10263/2574
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dc.contributor.authorMajumder, S-
dc.contributor.authorSur Kolay, Susmita-
dc.contributor.authorBhattacharya, Bhargab B-
dc.contributor.authorDas, S K-
dc.date.accessioned2011-09-19T11:13:59Z-
dc.date.available2011-09-19T11:13:59Z-
dc.date.issued2007-
dc.identifier.citationACM Transactions on design automation of electronic systemsV12,P141-159en_US
dc.identifier.urihttp://hdl.handle.net/10263/2574-
dc.language.isoenen_US
dc.subjectFloorplanningen_US
dc.subjectGlobal routingen_US
dc.subjectNetwork flowen_US
dc.subjectN P completenessen_US
dc.subjectBalanced bipartitioningen_US
dc.titleHierarchical partitioning of VLSI floorplans by staircasesen_US
dc.typeArticleen_US
Appears in Collections:Mathematics and Statistics

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