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Please use this identifier to cite or link to this item: http://hdl.handle.net/10263/3853
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dc.contributor.authorChakrabarti, S-
dc.contributor.authorDas, S-
dc.contributor.authorDas, D K-
dc.contributor.authorBhattacharya, Bhargab B-
dc.date.accessioned2012-05-07T18:50:53Z-
dc.date.available2012-05-07T18:50:53Z-
dc.date.issued2000-
dc.identifier.citationIEEE Transaction on CAD,V19,P1076-1081en_US
dc.identifier.urihttp://hdl.handle.net/10263/3853-
dc.language.isoenen_US
dc.subjectDelay faulten_US
dc.subjectSymmetric boolean functionen_US
dc.subjectSynthesis for testibilityen_US
dc.titleSynthesis of symmetric functions for path delay fault testabilityen_US
dc.typeArticleen_US
Appears in Collections:Computer Science

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