Please use this identifier to cite or link to this item:
http://hdl.handle.net/10263/4264
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Das, Nabanita | - |
dc.contributor.author | Dattagupta, Jayasree | - |
dc.date.accessioned | 2012-06-12T14:47:31Z | - |
dc.date.available | 2012-06-12T14:47:31Z | - |
dc.date.issued | 1996 | - |
dc.identifier.citation | Journal of system architecture,V42,P67-81 | en_US |
dc.identifier.uri | http://hdl.handle.net/10263/4264 | - |
dc.language.iso | en | en_US |
dc.subject | Multistage interconnection network | en_US |
dc.subject | Rearrangeable networks | en_US |
dc.subject | Unique path full access network | en_US |
dc.subject | The Benes network | en_US |
dc.subject | Fault tolerant routing | en_US |
dc.subject | Conflicts | en_US |
dc.title | Fault identification and routing in benes networks | en_US |
dc.type | Article | en_US |
Appears in Collections: | Electronics |
Files in This Item:
File | Description | Size | Format | |
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Binder2.pdf | 2.77 MB | Adobe PDF | View/Open |
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