Please use this identifier to cite or link to this item:
http://hdl.handle.net/10263/4373Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | De, Mallika | - |
| dc.contributor.author | Sinha, Bhabani P | - |
| dc.date.accessioned | 2012-06-14T17:37:34Z | - |
| dc.date.available | 2012-06-14T17:37:34Z | - |
| dc.date.issued | 1994 | - |
| dc.identifier.citation | IEEE transaction of computors,V43,P603-607 | en_US |
| dc.identifier.uri | http://hdl.handle.net/10263/4373 | - |
| dc.language.iso | en | en_US |
| dc.subject | Balanced ternary logic | en_US |
| dc.subject | Coloum compression | en_US |
| dc.subject | Ternary multiplication | en_US |
| dc.subject | Systolic architecture | en_US |
| dc.title | Fast Parallel algorithm for ternary multiplication using multivariate I L technology | en_US |
| dc.type | Article | en_US |
| Appears in Collections: | Electronics | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Binder2.pdf | 968.58 kB | Adobe PDF | View/Open |
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