Please use this identifier to cite or link to this item:
http://hdl.handle.net/10263/4466| Title: | fast parallel algorithms for binary multiplication and their implementation on systolic architecture |
| Authors: | Sinha, Bhabani P Srimani, Pradip K |
| Keywords: | Parallel algorithm Binary multiplication |
| Issue Date: | 1989 |
| Citation: | IEEE transaction on computers,V38,3,P424-431 |
| URI: | http://hdl.handle.net/10263/4466 |
| Appears in Collections: | Electronics |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Binder5.pdf | 1.53 MB | Adobe PDF | View/Open |
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