fast parallel algorithms for binary multiplication and their implementation on systolic architecture

Please use this identifier to cite or link to this item: http://hdl.handle.net/10263/4466

Full metadata record

DC Field	Value	Language
dc.contributor.author	Sinha, Bhabani P	-
dc.contributor.author	Srimani, Pradip K	-
dc.date.accessioned	2012-07-25T07:32:34Z	-
dc.date.available	2012-07-25T07:32:34Z	-
dc.date.issued	1989	-
dc.identifier.citation	IEEE transaction on computers,V38,3,P424-431	en_US
dc.identifier.uri	http://hdl.handle.net/10263/4466	-
dc.language.iso	en	en_US
dc.subject	Parallel algorithm	en_US
dc.subject	Binary multiplication	en_US
dc.title	fast parallel algorithms for binary multiplication and their implementation on systolic architecture	en_US
dc.type	Article	en_US
Appears in Collections:	Electronics

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