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Please use this identifier to cite or link to this item: http://hdl.handle.net/10263/4552
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dc.contributor.authorDasgupta, Partha Sarathi-
dc.contributor.authorSur Kolay, Susmita-
dc.contributor.authorBhattacharya, Bhargab B-
dc.date.accessioned2012-10-19T09:46:54Z-
dc.date.available2012-10-19T09:46:54Z-
dc.date.issued1998-09-
dc.identifier.citationIEEE Transactions on computer -Aided Design of Integrated Circuits and Systems,v.17,no.2,p.126-135en_US
dc.identifier.urihttp://hdl.handle.net/10263/4552-
dc.language.isoenen_US
dc.subjectAND-OR graph searchen_US
dc.subjectVLSI floorplaningen_US
dc.titleA unified approach to topology generation and optimal sizing of floorplansen_US
dc.typeArticleen_US
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