Please use this identifier to cite or link to this item:
http://hdl.handle.net/10263/5351| Title: | Fast parallel algorithm for ternary multiplication using multivalued IL technology |
| Authors: | De, Mallika Sinha, Bhabani P |
| Keywords: | Balanced ternary logic Column compression Precarry addition Systolic architecture Ternary multiplication |
| Issue Date: | May-1994 |
| Citation: | IEEETOC, v 43, no 5, p 603-607 |
| URI: | http://hdl.handle.net/10263/5351 |
| Appears in Collections: | Computer Science |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Fast parallel algorithm for ternary multiplication using multivalued IL technology-IEEETOC-43-5-1994 .pdf | 1.07 MB | Adobe PDF | View/Open |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.