Please use this identifier to cite or link to this item:
http://hdl.handle.net/10263/5433| Title: | Design of parity testable combinational circuits |
| Authors: | Bhattacharya, Bhargab B |
| Keywords: | Parity testable Combinational circuit Maximal supergates Single external test-mode pin |
| Issue Date: | 1989 |
| Citation: | IEEE Transactions on Computers,v.38 ,no.11 ,p.1580-1584 |
| URI: | http://hdl.handle.net/10263/5433 |
| Appears in Collections: | Computer Science |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| ITOC-38-11-1989-P1580-1584.pdf | 400.29 kB | Adobe PDF | View/Open |
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