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Please use this identifier to cite or link to this item: http://hdl.handle.net/10263/5433
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dc.contributor.authorBhattacharya, Bhargab B-
dc.date.accessioned2013-06-14T12:29:13Z-
dc.date.available2013-06-14T12:29:13Z-
dc.date.issued1989-
dc.identifier.citationIEEE Transactions on Computers,v.38 ,no.11 ,p.1580-1584en_US
dc.identifier.urihttp://hdl.handle.net/10263/5433-
dc.language.isoenen_US
dc.subjectParity testableen_US
dc.subjectCombinational circuiten_US
dc.subjectMaximal supergatesen_US
dc.subjectSingle external test-mode pinen_US
dc.titleDesign of parity testable combinational circuitsen_US
dc.typeArticleen_US
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