Please use this identifier to cite or link to this item:
http://hdl.handle.net/10263/5918| Title: | Logic design using digital summarion threshold-logic gates |
| Authors: | Pal, A |
| Keywords: | Logic design Digital summation Algorithms System |
| Issue Date: | 1983 |
| Citation: | IEE Proceedings, V.130. No.1, P 32-36 |
| URI: | http://hdl.handle.net/10263/5918 |
| Appears in Collections: | Computer Science |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| IP-130-1-1983-P32-36.pdf | 1.24 MB | Adobe PDF | View/Open |
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