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Please use this identifier to cite or link to this item: http://hdl.handle.net/10263/6199
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dc.contributor.authorNayagam N, Gomathi-
dc.date.accessioned2016-06-30T17:34:08Z-
dc.date.available2016-06-30T17:34:08Z-
dc.date.issued1996-
dc.identifier.citation65p.en_US
dc.identifier.urihttp://hdl.handle.net/10263/6199-
dc.descriptionDissertation under the supervision of Dr. Bhargab Bhattacharyaen_US
dc.language.isoenen_US
dc.publisherIndian Statistical Institute, Kolkataen_US
dc.relation.ispartofseriesDissertation;96-24-
dc.subjectVLSI design cycleen_US
dc.subjectCircuit designen_US
dc.subjectLogic synthesisen_US
dc.titleTesting and simulation involved in the circuit designen_US
dc.typeThesisen_US
Appears in Collections:Dissertations - M Tech (CS)

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