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Please use this identifier to cite or link to this item: http://hdl.handle.net/10263/6214
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dc.contributor.authorChattopadhyay, Nirmalya-
dc.date.accessioned2016-06-30T20:58:25Z-
dc.date.available2016-06-30T20:58:25Z-
dc.date.issued1997-
dc.identifier.citation43p.en_US
dc.identifier.urihttp://hdl.handle.net/10263/6214-
dc.descriptionDissertation under the supervision of Dr. Subhas C. Nandyen_US
dc.language.isoenen_US
dc.publisherIndian Statistical Institute, Kolkataen_US
dc.relation.ispartofseriesDissertation;97-41-
dc.subjectVLSI floorplanen_US
dc.subjectStaircase channelen_US
dc.subjectCrossing netsen_US
dc.subjectAlgorithmsen_US
dc.titleFloorplan equipartitioning using staircase channel minimizing the crossing netsen_US
dc.typeThesisen_US
Appears in Collections:Dissertations - M Tech (CS)

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