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Please use this identifier to cite or link to this item: http://hdl.handle.net/10263/6238
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dc.contributor.authorSwamy, Dhoss P-
dc.date.accessioned2016-07-01T19:12:17Z-
dc.date.available2016-07-01T19:12:17Z-
dc.date.issued1999-
dc.identifier.citation33p.en_US
dc.identifier.urihttp://hdl.handle.net/10263/6238-
dc.descriptionDissertation under the supervision of Dr. B.P. Sinhaen_US
dc.language.isoenen_US
dc.publisherIndian Statistical Institute, Kolkataen_US
dc.relation.ispartofseriesDissertation;99-66-
dc.subjectCoprocessorsen_US
dc.subjectRedundant radix-4en_US
dc.subjectArchitecture of RR-4en_US
dc.titleRedundant radix-4 coprocessor architecture implementationen_US
dc.typeThesisen_US
Appears in Collections:Dissertations - M Tech (CS)

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