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Please use this identifier to cite or link to this item: http://hdl.handle.net/10263/6364
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dc.contributor.authorBag, Amlan-
dc.date.accessioned2016-07-06T16:28:33Z-
dc.date.available2016-07-06T16:28:33Z-
dc.date.issued2007-
dc.identifier.citation38p.en_US
dc.identifier.urihttp://hdl.handle.net/10263/6364-
dc.descriptionDissertation under the supervision of Prof. Bhargab B. Bhattacharyaen_US
dc.language.isoenen_US
dc.publisherIndian Statistical Institute, Kolkataen_US
dc.relation.ispartofseriesDissertation;2007-200-
dc.subjectVLSI bipartitionen_US
dc.subjectStaircase channelen_US
dc.subjectBuffer insertionen_US
dc.subjectFloorplanen_US
dc.titleGeneral recursive staircase bipartition scheme for VLSI floor plan layout with simultaneous minimization of net crossoversen_US
dc.typeThesisen_US
Appears in Collections:Dissertations - M Tech (CS)

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