Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/6214
Title: Floorplan equipartitioning using staircase channel minimizing the crossing nets
Authors: Chattopadhyay, Nirmalya
Keywords: VLSI floorplan
Staircase channel
Crossing nets
Algorithms
Issue Date: 1997
Publisher: Indian Statistical Institute, Kolkata
Citation: 43p.
Series/Report no.: Dissertation;97-41
Description: Dissertation under the supervision of Dr. Subhas C. Nandy
URI: http://hdl.handle.net/123456789/6214
Appears in Collections:Dissertations

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