Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/6292
Title: Scan path architecture for low power testing
Authors: Srivastava, Praveen
Keywords: Scan design
Scan architecture
DTS
Low power testing
Issue Date: 2004
Publisher: Indian Statistical Institute, Kolkata
Citation: 35p.
Series/Report no.: Dissertation;2004-122
Description: Dissertation under the supervision of Prof. Bhargab B. Bhattacharya
URI: http://hdl.handle.net/123456789/6292
Appears in Collections:Dissertations

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