An efficient scan tree design for compact test pattern set

dc.contributor.author	Banerjee, S
dc.contributor.author	Roychowdhury, D
dc.contributor.author	Bhattacharya, Bhargab B
dc.date.accessioned	2011-08-04T12:25:16Z
dc.date.available	2011-08-04T12:25:16Z
dc.date.issued	2007
dc.identifier.citation	IEEE transaction on pattern analysis and machine intelligence,V29,9,P1590-1602	en_US
dc.identifier.uri	http://hdl.handle.net/10263/2293
dc.language.iso	en	en_US
dc.subject	Design for testability	en_US
dc.subject	Scan path	en_US
dc.subject	Space compaction	en_US
dc.subject	Stuck at faults	en_US
dc.subject	Testing	en_US
dc.subject	Very large scale integration	en_US
dc.title	An efficient scan tree design for compact test pattern set	en_US
dc.type	Article	en_US