Hierarchical partitioning of VLSI floorplans by staircases

dc.contributor.author	Majumder, S
dc.contributor.author	Sur Kolay, Susmita
dc.contributor.author	Bhattacharya, Bhargab B
dc.contributor.author	Das, S K
dc.date.accessioned	2011-09-19T11:13:59Z
dc.date.available	2011-09-19T11:13:59Z
dc.date.issued	2007
dc.identifier.citation	ACM Transactions on design automation of electronic systemsV12,P141-159	en_US
dc.identifier.uri	http://hdl.handle.net/10263/2574
dc.language.iso	en	en_US
dc.subject	Floorplanning	en_US
dc.subject	Global routing	en_US
dc.subject	Network flow	en_US
dc.subject	N P completeness	en_US
dc.subject	Balanced bipartitioning	en_US
dc.title	Hierarchical partitioning of VLSI floorplans by staircases	en_US
dc.type	Article	en_US