dc.contributor.author | Chakrabarti, S | |
dc.contributor.author | Das, S | |
dc.contributor.author | Das, D K | |
dc.contributor.author | Bhattacharya, Bhargab B | |
dc.date.accessioned | 2012-05-07T18:50:53Z | |
dc.date.available | 2012-05-07T18:50:53Z | |
dc.date.issued | 2000 | |
dc.identifier.citation | IEEE Transaction on CAD,V19,P1076-1081 | en_US |
dc.identifier.uri | http://hdl.handle.net/10263/3853 | |
dc.language.iso | en | en_US |
dc.subject | Delay fault | en_US |
dc.subject | Symmetric boolean function | en_US |
dc.subject | Synthesis for testibility | en_US |
dc.title | Synthesis of symmetric functions for path delay fault testability | en_US |
dc.type | Article | en_US |