Parallel system design  for time delay neural networks

dc.contributor.author	Chang, David
dc.contributor.author	Pal, Sankar K
dc.date.accessioned	2012-05-08T15:52:48Z
dc.date.available	2012-05-08T15:52:48Z
dc.date.issued	2000
dc.identifier.citation	IEEE Transaction system man and cybernetics,Pt-C ,Application and reviews,V30,P265-275	en_US
dc.identifier.uri	http://hdl.handle.net/10263/3877
dc.language.iso	en	en_US
dc.subject	Parallel computing	en_US
dc.subject	Pipeline architecture	en_US
dc.subject	Time delay neural network	en_US
dc.subject	Speech recognition	en_US
dc.title	Parallel system design for time delay neural networks	en_US
dc.type	Article	en_US