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Fast parallel algorithm for ternary multiplication using multivalued IL technology
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| dc.contributor.author | De, Mallika | |
| dc.contributor.author | Sinha, Bhabani P | |
| dc.date.accessioned | 2013-05-07T12:09:41Z | |
| dc.date.available | 2013-05-07T12:09:41Z | |
| dc.date.issued | 1994-05 | |
| dc.identifier.citation | IEEETOC, v 43, no 5, p 603-607 | en_US |
| dc.identifier.uri | http://hdl.handle.net/10263/5351 | |
| dc.language.iso | en | en_US |
| dc.subject | Balanced ternary logic | en_US |
| dc.subject | Column compression | en_US |
| dc.subject | Precarry addition | en_US |
| dc.subject | Systolic architecture | en_US |
| dc.subject | Ternary multiplication | en_US |
| dc.title | Fast parallel algorithm for ternary multiplication using multivalued IL technology | en_US |
| dc.type | Article | en_US |
