Design of parity testable combinational circuits

dc.contributor.author	Bhattacharya, Bhargab B
dc.date.accessioned	2013-06-14T12:29:13Z
dc.date.available	2013-06-14T12:29:13Z
dc.date.issued	1989
dc.identifier.citation	IEEE Transactions on Computers,v.38 ,no.11 ,p.1580-1584	en_US
dc.identifier.uri	http://hdl.handle.net/10263/5433
dc.language.iso	en	en_US
dc.subject	Parity testable	en_US
dc.subject	Combinational circuit	en_US
dc.subject	Maximal supergates	en_US
dc.subject	Single external test-mode pin	en_US
dc.title	Design of parity testable combinational circuits	en_US
dc.type	Article	en_US