Logic design using digital summarion threshold-logic gates

dc.contributor.author	Pal, A
dc.date.accessioned	2014-06-13T09:40:24Z
dc.date.available	2014-06-13T09:40:24Z
dc.date.issued	1983
dc.identifier.citation	IEE Proceedings, V.130. No.1, P 32-36	en_US
dc.identifier.uri	http://hdl.handle.net/10263/5918
dc.language.iso	en	en_US
dc.subject	Logic design	en_US
dc.subject	Digital summation	en_US
dc.subject	Algorithms	en_US
dc.subject	System	en_US
dc.title	Logic design using digital summarion threshold-logic gates	en_US
dc.type	Article	en_US