Floorplan equipartitioning using staircase channel minimizing the crossing nets

Chattopadhyay, Nirmalya

dc.contributor.author	Chattopadhyay, Nirmalya
dc.date.accessioned	2016-06-30T20:58:25Z
dc.date.available	2016-06-30T20:58:25Z
dc.date.issued	1997
dc.identifier.citation	43p.	en_US
dc.identifier.uri	http://hdl.handle.net/10263/6214
dc.description	Dissertation under the supervision of Dr. Subhas C. Nandy	en_US
dc.language.iso	en	en_US
dc.publisher	Indian Statistical Institute, Kolkata	en_US
dc.relation.ispartofseries	Dissertation;97-41
dc.subject	VLSI floorplan	en_US
dc.subject	Staircase channel	en_US
dc.subject	Crossing nets	en_US
dc.subject	Algorithms	en_US
dc.title	Floorplan equipartitioning using staircase channel minimizing the crossing nets	en_US
dc.type	Thesis	en_US