Effect of circuit structure on path delay fault testability in VLSI design

Sarkar, Biplab

dc.contributor.author	Sarkar, Biplab
dc.date.accessioned	2016-07-01T17:29:14Z
dc.date.available	2016-07-01T17:29:14Z
dc.date.issued	1998
dc.identifier.citation	24p.	en_US
dc.identifier.uri	http://hdl.handle.net/10263/6234
dc.description	Dissertation under the supervision of Prof. Bhargab B. Bhattacharya, ACM Unit	en_US
dc.language.iso	en	en_US
dc.publisher	Indian Statistical Institute, Kolkata	en_US
dc.relation.ispartofseries	Dissertation;98-61
dc.subject	Design for testability	en_US
dc.subject	Path model	en_US
dc.subject	Testability preserving transformations	en_US
dc.subject	Testability improving transformations	en_US
dc.title	Effect of circuit structure on path delay fault testability in VLSI design	en_US
dc.type	Thesis	en_US