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Algorithm for mapping boolean network to LUT based FPGAs
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Algorithm for mapping boolean network to LUT based FPGAs
Bhattacharyya, Jayasri
URI:
http://hdl.handle.net/10263/6256
Date:
2001
Description:
Dissertation under the supervision of Dr. Sushmita Sur-Kolay
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Dissertations - M Tech (CS)
M Tech (Computer Science)
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