Algorithm for mapping boolean network to LUT based FPGAs

dc.contributor.author	Bhattacharyya, Jayasri
dc.date.accessioned	2016-07-01T21:36:48Z
dc.date.available	2016-07-01T21:36:48Z
dc.date.issued	2001
dc.identifier.citation	47p.	en_US
dc.identifier.uri	http://hdl.handle.net/10263/6256
dc.description	Dissertation under the supervision of Dr. Sushmita Sur-Kolay	en_US
dc.language.iso	en	en_US
dc.publisher	Indian Statistical Institute, Kolkata	en_US
dc.relation.ispartofseries	Dissertation;2001-84
dc.subject	FPGA	en_US
dc.subject	DAG-map algorithms	en_US
dc.subject	Boolean network	en_US
dc.subject	Mapping	en_US
dc.title	Algorithm for mapping boolean network to LUT based FPGAs	en_US
dc.type	Thesis	en_US