Scan path architecture for low power testing

dc.contributor.author	Srivastava, Praveen
dc.date.accessioned	2016-07-04T20:38:20Z
dc.date.available	2016-07-04T20:38:20Z
dc.date.issued	2004
dc.identifier.citation	35p.	en_US
dc.identifier.uri	http://hdl.handle.net/10263/6292
dc.description	Dissertation under the supervision of Prof. Bhargab B. Bhattacharya	en_US
dc.language.iso	en	en_US
dc.publisher	Indian Statistical Institute, Kolkata	en_US
dc.relation.ispartofseries	Dissertation;2004-122
dc.subject	Scan design	en_US
dc.subject	Scan architecture	en_US
dc.subject	DTS	en_US
dc.subject	Low power testing	en_US
dc.title	Scan path architecture for low power testing	en_US
dc.type	Thesis	en_US