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General recursive staircase bipartition scheme for VLSI floor plan layout with simultaneous minimization of net crossovers

General recursive staircase bipartition scheme for VLSI floor plan layout with simultaneous minimization of net crossovers

Bag, Amlan
URI: http://hdl.handle.net/10263/6364
Date: 2007

Description:

Dissertation under the supervision of Prof. Bhargab B. Bhattacharya

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