General recursive staircase bipartition scheme for VLSI floor plan layout with simultaneous minimization of net crossovers

Bag, Amlan

dc.contributor.author	Bag, Amlan
dc.date.accessioned	2016-07-06T16:28:33Z
dc.date.available	2016-07-06T16:28:33Z
dc.date.issued	2007
dc.identifier.citation	38p.	en_US
dc.identifier.uri	http://hdl.handle.net/10263/6364
dc.description	Dissertation under the supervision of Prof. Bhargab B. Bhattacharya	en_US
dc.language.iso	en	en_US
dc.publisher	Indian Statistical Institute, Kolkata	en_US
dc.relation.ispartofseries	Dissertation;2007-200
dc.subject	VLSI bipartition	en_US
dc.subject	Staircase channel	en_US
dc.subject	Buffer insertion	en_US
dc.subject	Floorplan	en_US
dc.title	General recursive staircase bipartition scheme for VLSI floor plan layout with simultaneous minimization of net crossovers	en_US
dc.type	Thesis	en_US