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Architectures for computer vision : from algorithm to chip with Verilog / Hong Jeong.

By: Material type: TextTextPublication details: Singapore : John Wiley, ©2014.Description: xv, 450 p. : ill. ; 26 cmISBN:
  • 9781118659182
Subject(s): DDC classification:
  • 621.39 23 J54
Contents:
1. Introduction -- 2. Verilog HDL, communication, and control -- 3. Processor, memory, and array -- 4. Verilog vision simulator -- 5. Energy function -- 6. Stereo vision -- 7. Motion and vision modules -- 8. Relaxation for energy minimization -- 9. Dynamic programming for energy minimization -- 10. Belief propagation and graph cuts for energy minimization -- 11. Relaxation for stereo matching -- 12. Dynamic programming for stereo matching -- 13. Systolic array for stereo matching -- 14. Belief propagation for stereo matching.
Summary: This book provides comprehensive coverage of 3D vision systems, from vision models and state-of-the-art algorithms to their hardware architectures for implementation on DSPs, FPGA and ASIC chips, and GPUs. It aims to fill the gaps between computer vision algorithms and real-time digital circuit implementations, especially with Verilog HDL design.
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Holdings
Item type Current library Call number Status Date due Barcode Item holds
Books ISI Library, Kolkata 621.39 J54 (Browse shelf(Opens below)) Available 137079
Total holds: 0

Includes bibliographical references and index.

1. Introduction --
2. Verilog HDL, communication, and control --
3. Processor, memory, and array --
4. Verilog vision simulator --
5. Energy function --
6. Stereo vision --
7. Motion and vision modules --
8. Relaxation for energy minimization --
9. Dynamic programming for energy minimization --
10. Belief propagation and graph cuts for energy minimization --
11. Relaxation for stereo matching --
12. Dynamic programming for stereo matching --
13. Systolic array for stereo matching --
14. Belief propagation for stereo matching.

This book provides comprehensive coverage of 3D vision systems, from vision models and state-of-the-art algorithms to their hardware architectures for implementation on DSPs, FPGA and ASIC chips, and GPUs. It aims to fill the gaps between computer vision algorithms and real-time digital circuit implementations, especially with Verilog HDL design.

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