TY  - BOOK
AU  - Mondal,Manobendra Nath
TI  - Memristive crossbars: ALU design, testing, and fault analysis for neuromorphic applications
U1  - 621.3815 23
PY  - 2023///
CY  - Kolkata
PB  - Indian Statistical Institute, 
KW  - Memristor Model
KW  - Memristor-Based Crossbar (MBC)
KW  - Memristive Hybrid Crossbar
KW  - Computation-in-Memory (CIM)
KW  - Memristive Arithmetic Logic Unit (ALU)
KW  - Memristor Fault Model
KW  - Memristive Crossbar Testing
KW  - Sneak-Path Testing
KW  - Bipartite Matching
KW  - Latin Square
KW  - Memristive Neuromorphic Computing Architecture (MNCA)
KW  - Fault Sensitivity Analysis
KW  - Fault-Tolerance
N1  - Thesis (Ph.D.) - Indian Statistical Institute, 2023; Includes bibliography; Introduction and scope of the thesis -- Review of related works -- Design of memristive adders using differential current sensing -- Memristive crossbar architectures for subtractor multiplier and logical modules -- Test optimization in full memristive crossbars --  Test optimization in incomplete memristive crossbars -- Analysis of fault sensitivity in memristive neural architectures --  Conclusions and future directions; Guided by Prof. Susmita Sur-Kolay and Prof. Bhargab B. Bhattacharya
N2  - In 1971, Professor Leon Chua introduced the notion of a memristor, the fourth fundamental passive circuit component alongside resistor, capacitor, and inductor. The resistance of this two-terminal device depends on the current through it; thereby a memristor is similar to a resistor with memory. In 2008, a group of researchers at HP Labs built the first memristor successfully and demonstrated its characteristic resistance-switching behaviour. Its unique properties and compatibility with CMOS technology has made it a powerful circuit element and has significantly influenced design paradigms.
Recent developments have shown that memristors are promising for designing memory and logic subsystems, which can store multiple states of memory by utilizing the analog variation of resistance in the cells. By combining CMOS components with memristor cells, hybrid systems can be created where CMOS components can perform computation-in-memory (CIM), while memristor cells can store data in a non-volatile manner. Memristor-based crossbars (MBCs) realised as a 2D-array of memristors, have been particularly effective for performing certain types of computations, such as vector-matrix multiplication (VMM) and vector outer product, which are crucial in neuromorphic computing systems. Developing practical and reliable memristive crossbar-based systems for various applications still poses significant challenges which can hinder their performance and scalability. This thesis tackles several challenges head-on, offering innovative solutions that elevate their performance, reliability, and scalability.
In this thesis, we introduce novel designs for an arithmetic logic unit (ALU) that utilize differential currents passing through a hybrid-memristor crossbar network. The ALU performs integer addition, subtraction, multiplication, and logical operations in the binary domain, using both analog and digital components.
Next, we envisage a 2D memristor crossbar as a network and identify certain paths that are suitable for fault sensitization. In order to optimize testing time for full-size square and rectangular memristive crossbars, we propose a path-based technique guided by maximum matching in bipartite graphs. We also employ an integer linear programming (ILP) formulation to solve the problem for a general crossbar.
Finally, we present a thorough analysis of the impact of various hard faults of memristive crossbars on accuracy of different neuromorphic architectures for different datasets This study is critical as comprehending the effects of such faults and variations can enhance the reliability and efficacy of fault-tolerant memristor based neuromorphic computing systems with resource constraints.
Overall, this thesis contributes to advancing memristor-based computing systems by addressing efficient ALU design, test time optimization, and analyzing the impact of faults on neuromorphic architectures. The findings provide valuable insights to improve the reliability and performance of future fault-tolerant memristor-based systems across a wide range of applications
UR  - http://dspace.isical.ac.in:8080/jspui/handle/10263/7426
ER  -